1. Field of the Invention
The present invention relates to a semiconductor memory device such as a flash-type EEPROM (Electrically Erasable/Programmable Read Only Memory) and a method of manufacturing the same.
2. Description of the Related Art
A flash-type EEPROM conventionally used is configured as shown in FIGS. 14, 15, 16 and 17. FIG. 14 is a schematic plan view of the flash-type EEPROM, and FIGS. 15, 16 and 17 are sectional views taken along the lines XV--XV, XVI--XVI, and XVII--XVII of FIG. 14.
N.sup.+ -type drain diffusion regions 1 and N.sup.+ -type source diffusion regions 2 are formed in a P-type semiconductor substrate 10 with channel regions 3 defined between the diffusion regions 1 and 2. A floating gate 5 in an electrically floating state is formed on each of the channel regions 3 with a tunnel oxide film 4 interposed between them. A control gate 8 acting as a word line is superposed over the floating gate 5 with an insulating film 6 sandwiched between them. Either of the floating gate 5 and the control gate 8 is made of, for example, polycrystalline silicon film. Reference numeral 7 denotes low concentration impurity diffusion layers used for enhancing sustainable voltage of the source diffusion regions 1.
A layer insulating film 9 is formed over a surface of the substrate 10 on which the above-mentioned various components such as the control gate 8 are formed. Contact holes 11 are formed above the drain diffusion regions 1 in the layer insulating film 9. On a surface of the layer insulating film 9, aluminum wirings 12 serving as bit lines are formed in contact with the drain diffusion regions 1 in the contact hole 11. Reference numeral 13 designates field oxide films for isolating cells from one another.
Each drain diffusion region 1 and each source diffusion region 2 are shared with adjacent memory cells. The source diffusion regions 2 disposed along word lines (control gates 8) are interconnected by source lines 14. The source lines 14 are formed in the substrate 10 by impurity diffusion simultaneous with forming the source diffusion regions 2.
When writing voltage at a positive high level (e.g., 12 V) is applied to the control gate 8 and also positive high voltage (e.g., 7 V) is applied to the drain diffusion region 1, electrons are accelerated from the source diffusion region 2 toward the drain diffusion region 1. Simultaneously, a strong electric field caused in the boundary of each drain diffusion region 1 produces hot electrons, which pass through the tunnel oxide film 4 and are injected into the floating gate 5. In this way, writing is effected. When high voltage reverse in polarity to the voltage in the writing is applied between the control gate 8 and the substrate 10, electrons are pulled out of the floating gate 5. In this way, erasing is effected.
A threshold level of the voltage to be applied to the control gate 8 in order to electrically connect a source and a drain, takes two different values depending upon whether the electrons exist in the floating gate 5. Sense voltage which has an intermediate level between the two different threshold levels is applied and then connection/disconnection between the source and the drain is checked, and thus, reading information can be effected.
Because of the electrically floating state of the floating gate 5, the quantity of electric charge injected therein is not varied unless the writing voltage or the erasing voltage is applied thereto, and therefore, storing data can be effected in a non-volatile manner.
Such a flash-type EEPROM is made in a manner as described below. A field oxide film 13 is formed on a surface of the substrate 10 by a LOCOS (LOCal Oxidation of Silicon) method, and then, the tunnel oxide film 4 is formed over the entire surface of the substrate 10. In this situation, the floating gate 5 is formed by depositing polycrystalline silicon, adding phosphorus as impurity to gain conductivity, and then patterning it.
Then, the insulating film 6 is formed, and after deposition of polycrystalline silicon, addition of phosphorus, and patterning, the control gates 8 acting as word lines is formed. The source diffusion regions 2 and the source lines 14 are to be formed later by implanting ions in regions between the field oxide films 13. For that purpose, some components such as the control gates 8 must be formed in position without protruding into an area between the field oxide films 13. Hence, allowing for an accuracy of mask alignment and other factors, the components such as the control gates 8 are formed in positions a distance .DELTA.L receding from edges of the field oxide films 13, as shown in FIG. 17. If the control gates 8 are formed in a position protruding from the edges of the field oxide films 13, each of the source lines 14 is reduced in width to have an insufficient cross-sectional area, and this may cause a high resistance therein.
After the control gates 8 are formed, phosphorus ions are implanted to form the low concentration diffusion layers 7 surrounding the source diffusion regions 2. Then, arsenic ions are implanted with masks of the field oxide films 13 and the control gates 8, and thereby the N.sup.+ -type source diffusion regions 2, the N.sup.+ -type drain diffusion regions 1 and the source lines 14 are formed.
Then, the substrate 10 is covered with the layer insulating film 9, and the contact holes 11 are formed. After that, the aluminum wiring 12 acting as bit lines are formed and patterned.
In the above-mentioned flash-type EEPROM, however, degree of integration therein is restricted, and hence, there arises a disadvantage that miniaturization of the whole memory device is difficult. More specifically, the field oxide films 13 are used to isolate elements from each other in the abovementioned flash-type EEPROM. Hence, it is necessary to make the oxide films extend to a level deep enough from the surface of the substrate to perfectly isolate the elements, and this is why the oxide films 13 must be made thick. With the oxide films thickened, their width along the surface of the substrate 10 is necessarily increased, and naturally, a distance L1 between the bit lines (see FIG. 14) becomes large to some extent. This prevents an enhancement of integration in the memory device.
Moreover, as described above, since the source diffusion regions 2 and the source lines 14 are formed by ion implantation after the word lines (control gates 8) are formed, the word lines must be formed in positions receding from the edges of the field oxide films 13. In other words, in a configuration where the source lines 14 formed by the ion implantation extend in the semiconductor substrate 10 between the adjacent word lines (control gates 8), reduction of a distance L2 between the word lines is restricted. This also prevents an enhancement of integration in the memory device.
In addition to that, in a process of manufacturing the above flash-type EEPROM, although both the floating gate 5 and the control gate 8 are formed of polycrystalline silicon film, they are patterned individually. Hence, there arises another disadvantage that the manufacturing process is complicated.